The subject matter of the present application relates to a microelectronic package including stacked microelectronic units, and to methods of fabricating the package.
Semiconductor chips are flat bodies with contacts disposed on a front surface that are connected to internal electrical circuitry of the chip itself. The chips are typically packaged to form a microelectronic package having terminals that are electrically connected to the package's contacts. The terminals of the package may then be connected to an external microelectronic component, such as a circuit panel.
It is often desirable to package microelectronic packages in a “stack” arrangement, i.e., where plural microelectronic packages, each including at least one semiconductor chip, are placed one on top of another, to save space. In a stacked chip package structure or Package-on-Package (“PoP”), the chips of the respective packages can be mounted to occupy a surface area that is less than the total surface area of all the chips. The reduced area of the chips of the PoP can result in very efficient utilization of area on a printed circuit board (“PCB”) to which the chips of the PoP can eventually be attached.
Typically, microelectronic packages included in a PoP have a size large enough to permit testing of the chips of the individual packages at chip contacts thereof, before the packages are joined in a stacked arrangement to form the PoP. In addition, in some PoPs, conductive structures electrically interconnect chip contacts of the chips of the respective packages with each other and such conductive structure may have a length that causes high parasitics between the packages, which is undesirable.
Further improvements are, therefore, desirable in the art of producing a microelectronic package including stacked microelectronic units, each of the units including a microelectronic element such as a semiconductor chip, that can be connected to a microelectronic component external to the microelectronic package.